1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly, to processes related to forming through silicon vias (TSVs).
2. Related Art
Through silicon vias (TSVs) are vias etched through a substrate, e.g., a silicon (Si) wafer. TSVs may be used, for example, to allow wafer-to-wafer interconnect schemes such as those compatible with three dimensional wafer-level packaging. Openings for TSVs typically include an enlarged portion near an upper surface so that the opening can be more readily filled with a conductor. Current processes use at least two masks to form the TSV opening: a first mask used to open any layer over the substrate and open an upper portion of the substrate (e.g., silicon), and a second mask to open a lower portion of the substrate. In some cases, a third mask is used to create pre-metallization openings to ensure metallization level conductor alignment with the TSV.